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RITES – Resilient IT Infrastructures
Research area
Our society is becoming increasingly dependent on complex IT infrastructures and services. IT systems are already the most complex systems built by mankind, and their scale and complexity is increasing all the time. Complexity is escalating at all levels of technology stack — from application and service level till underlying implementation technology. Currently, the underlying technologies (i.e. processor architectures, and silicon technologies) are undergoing big leaps, from comparatively straightforward architectures (single-core) with deterministic behaviour, to complex architectures (heterogeneous many-core) with non-deterministic behaviour, due to changes in silicon yield etc.
TUCS is in a unique position to address these challenges in a unified way, since TUCS possesses competence of a cross-cutting nature that spans from highly abstract service modelling level to the hardware implementation platform. The partners of the research programme have strong track record in the corresponding fields.
Research goal
The research programme aims to address the challenges of complex IT infrastructures by targeting solutions along the following important themes, for which the participating research groups have a long track record of research achievements.
Adaptability
The challenge in future ICT-systems is that their application loads will vary highly at the same time as the available computing capabilities may vary over time. To achieve efficiency in different areas (energy, performance, cost, etc.), the application must be able to adapt itself to the environment, and to the capabilities available. The main challenges in this area lie in designing adaptable system architectures, as well as coming up with good adaptation strategies.
Future multi-core systems will exploit heterogeneous networked architectures and run dynamic loads created by future application scenarios. Run-time management of these systems requires a high degree of scalability and adaptivity from both the underlying hardware platform and the operating system or middle-ware of the platform. Distributed (decentralized) solutions need to be found for implementing such management functions. We focus on self-aware computing platforms and embedded storage systems that are energy proportional, i.e., their energy-efficiency remains high independently of the offered load. More specifically, we develop adaptive control and management approaches that enable efficient self-adaptation of the platform according to the dynamically changing computational load.
Efficiency
Efficiency is a key constraint in the construction of future ICT-systems. The construction itself must be cost efficient (lean), that is one should both do the right system and do the system in a right way, and avoid all unnecessary costs to achieve good time to market. This requires lean processes, but also cost effective approaches to verify and validate the proposed solutions. Lean processes, model-driven design, and formal methods are all part of the palette of approaches that have been successfully applied to system construction by the partners.
Efficiency is also important in the deployment of the system. This is specially challenging in the case of adaptable systems that need to provision resources dynamically based on the current needs. The system must be energy-efficient, and it must not underprovision or overprovision resources because this leads to low performance or high operation costs.
Foundations of Software Engineering
Theoretically well-founded techniques for software construction, both in the large and in the small, are a necessity for the production of highly reliable and functionally correct software systems. Our research in this area concerns program correctness, semantics, and formal methods. We focus on two main techniques: invariant-based programming, a correct-by-construction imperative programming methodology, and stepwise feature introduction, a rigorous extension mechanism for layered software architectures. These techniques are based on lattice theory, and provide a sound theoretical foundation on which applied software engineering methods can be built.
Teaching Programming
New correctness-oriented programming paradigms (such as invariant-based programming) coupled with the powerful automatic reasoning tools, promise to increase the quality of software but at the same time demand stronger mathematical and logical reasoning skills from the practitioner compared to the traditional approaches. Our focus in this area is on increasing the role of formal specification and verification techniques in the skillset of the next generation of software engineers. We strive towards this goal by teaching hands-on methods for correct-by-construction program development as early as possible, and couple them with strong theorem prover support to automate the verification process as far as possible.
Intentionality
To achieve efficiency in design and implementation, the description languages and abstractions used for describing systems need to be more problem oriented. The description language is the user-interface to the problem domain, and must be able to describe all the knowledge about the system available to the designer. More importantly it must be possible to describe the design intent of the designer. Therefore new paradigms for programming (e.g. dataflow languages, PRAM models), and new paradigms for system specification (e.g. event-B, metamodelling based DSL’s) have been introduced. Such paradigms are being actively developed within the programme, and they form one of the basic building blocks for the efficient development of scalable, resilient and adaptable IT-systems.
Scalability
Scalability is the ability of a system to handle growing amount of work in a capable manner or its ability to be enlarged to accommodate that growth. The scalability requirement is challenging because for a system to be scalable on both of these axes, the system platform must provide efficient ways of adapting to the current workload, something that requires run-time monitoring, and learning from past behaviours, while at the same time be implemented in a way that when new capacity (hardware) is added the system automatically takes this into account. Solutions already exists for some of these issues in the domain of web-services, while for other areas, e.g. radio algorithms the problem is yet unsolved. In particular for radio algorithms, improvements in architecture and hardware capacity usually result in a redesign of the whole system. Indeed one of the big challenges in this area is Performance Portability the ability to provide solutions that retain their performance over several hardware generations.
Resilience
Resilience is a central issue for the dependable systems. It is on the one hand a design problem, where one needs to handle system complexity, to secure the safety-critical and fault tolerant functioning, and on the other hand a platform problem, where the system should provide a number of implementation primitives to handle faults.
The work in this theme will focus on modelling safety-critical and fault tolerant systems from various domains – from traditional control systems to self-adapting multi-agent applications. We work on interfacing formal models with safety analysis techniques, creating patterns and process guidelines for modelling various aspects of dependability as well as proof-based verification and model-checking of essential dependability properties. We are also actively involved into extending refinement-based development method with stochastic reasoning and integration with probabilistic model checking. Furthermore the work will involve research around specific implementation techniques that the platform can provide to guarantee certain resiliency properties. Such techniques include forms of task migration and run-time updating, virtualization, and hardware fault detection.
Programme leader
Participating TUCS Research Units
- Embedded Computer and Electronic Systems (ECES)
- Embedded Systems Laboratory (ESLAB)
- Distributed Systems Laboratory (DS Lab)
- Software Construction Laboratorium
- Software Development Laboratory (SwDev)
- Software Engineering Laboratory (SE Lab)
Steering group
Ralph-Johan Back Ville Leppänen Johan Lilius Luigia Petre Juha Plosila Ivan Porres Elena Troubitsyna Marina Waldén Jan WesterholmActivities
- 17.3.2017: guest lecture: Prof. Antonio Augusto Fröhlich (Federal University of Santa Catarina, Brazil)
A Safer Internet of Cyber-Physical Things
The talk will be given at 12:15 in meeting rooms Mänty and Honka, Agora building (4th floor).
Abstract: The Internet of Things is a central element of Ubiquitous Computing and Smart Environments and recently became subject of intense academic research. The potential for services around the theme has been demonstrated by numerous projects and is now also attracting important sectors of the economy. However, most demonstrations of IoT presented thus far makes use of technologies developed for the ordinary Internet and for SmartPhones. Assuming that each object connected to the Internet will feature an ordinary TCP/IP stack implemented on the same premises of the original Internet is certainly a mistake, especially considering aspects such as security, power consumption, size, and cost. Moreover, the IP protocol itself, the driving force of the technological revolution we live, does not encompasses the notions of space and time that are so crucial to the emerging technology and inherent to Cyber-Physical Systems. UFSC's EPOSMote provides an open hardware and software platform for IoT research. Its main goal is to investigate and demonstrate alternatives to the Internet legacy for a Trustful Internet of Cyber-Physical Things. The mote was designed around a modular architecture, with interchangeable components in four layers: processing (AVR8, ARM7 and Cortex-M), communication (IEEE 802.15.4 and PLC), I/O (various types of sensors, leds, buttons, USB, serial, and J-Tag) and energy (battery, USB and photovoltaics). Modules can be easily tailored to specific applications following the philosophy of Application-driven Embedded System Design (ADESD). This talk presents the project, its role in IoT research, cyber-physical applications currently under development, and recent achievements toward a trustful cross-layer communication protocol for IoT.
Bio: Dr. Antonio Augusto Fröhlich is currently an Associate Professor at the Federal University of Santa Catarina (UFSC), where he has been leading the Software/Hardware Integration Lab (LISHA) since 2001. With a PhD degree in Computer Engineering from the Technical University of Berlin, he has coordinated a number of R&D projects on embedded systems, including the ALTATV Open, Free, Scalable Digital TV Platform and the CIA² research network on Smart Cities and the Internet of Things. Major contributions from these projects materialized within the Brazilian Digital Television System (SBTVD) and Wireless Sensor Network technology for Energy Distribution, Smart Cities, and Precision Agriculture. Dr. Fröhlich is member of ACM, IEEE, and SBC. - 30.1.2014: guest lecture: Dr. Tuan Anh Trinh (Budapest University of Technology and Economics, Hungary)
Energy efficiency and performance trade-off in communication networks
Dealing with energy efficiency typically points at savings in one or the other way. Saving communication resources is typically associated with compromises regarding communication quality. On this background, the talk focuses on (and somehow questions) the needs for trading off between energy efficiency and quality of servies (QoS) and Quality of Experience (QoE). To this end, we will address energy efficiency metrics in communication networks on the one hand, and identify the views of users upon energy consumption in the context of QoS/QoE on the other hand. We will illustrate possible solutions, tools and techniques at different network layers to improve energy efficiency in communications networks without compromising QoS/QoE. Case studies will be provided with respect to mobile wireless networks (in particular LTE networks), data center networks and embedded systems.
Host: ES Lab - 4.12.2013: guest lecture: Dr. Jeanette Heidenberg (Ericsson)
On Software Architecture
Host: DS Lab - 21.11.2013: guest lecture: Prof. Kai Koskimies (University of Tampere)
Software architecture evaluation – methods, experiences, issues
Host: DS Lab - 11.11.–11.12.2013: research visit: M.Sc. Iulia Banu (University of Bucharest, Romania)
Host: DS Lab - 7.11.2013: guest lecture: Dr. Joonas Lehtinen (Vaadin)
Notes on Architecture
Host: DS Lab - 10.–14.6.2013: conference: iFM 2013: 10th International Conference on integrated Formal Methods
Applying formal methods may involve modeling different aspects of a system which are best expressed using different formalisms. Correspondingly, different analysis techniques may be used to examine different system views, different kinds of properties, or, simply in order to cope with the sheer complexity of the system. The iFM conference series seeks to further research into hybrid approaches to formal modeling and analysis; i.e., the combination of (formal and semi-formal) methods for system development, regarding modeling and analysis, and covering all aspects from language design through verification and analysis techniques to tools and their integration into software engineering practice.
http://www.it.abo.fi/iFM2013/
Host: Luigia Petre - 31.5.2013: guest lecture: Professor Shashi Kumar (Jönköping University)
“Routing Algorithms for Partially Regular and Hierarchical Networks on Chip”
Network on Chip (NoC) is getting accepted by semiconductor industry as a preferred interconnection choice for implementing multi-core and multi-processor systems on chip. The regular mesh topology Network on Chip (NoC) architecture continues to be the most popular with researchers and manufacturers since it leads to deterministic electrical properties for the links. However, a weakness of the regular mesh topology is its inability to efficiently support cores of different sizes. In a typical multi-core SoC, there is a wide variation in the sizes of cores. One solution to this problem is to allot multiple slots (or rectangular regions) to oversized cores. This solution leads to more efficient use of chip area but introduces irregularity in the network. This irregularity implies that the standard routing algorithms for regular mesh topology are no more useful. We will present two solutions to design of deadlock free and efficient routing algorithms for such partially regular networks. Our attempt to solve this particular situation lead us to propose a methodology of designing efficient and deadlock free routing algorithm which is topology independent. We call this as APplication Specific Routing Algorithm (APSRA) design methodology.
In consistent with the development of electronics in the past, the systems of today will become components tomorrow. In the same sense, the components for future SoCs will be multi-core systems with their local networks connecting the cores. Therefore, a future system will be organized as a hierarchical NoC, consisting of possibly heterogeneous sub-networks as components. Designing deadlock free and efficient routing algorithms for such networks brings new challenges. We will describe HiRA, which is a methodology for design of deadlock free routing algorithms for hierarchical NoCs.
Host: ECES - 22.4.2013: guest lecture: Professor Thomas Hollstein (Tallin University of Technology, Estonia)
“Challenges for Application Deployment on Many-Core Architectures under Mixed Criticality Aspects”
Currently computer architectures are ungoing one of the largest paradigm shifts since the invention of the microprocessor. The scaling of classical computer architectures (based on concentrated multi-core processors) is limited due to the bottleneck of sharing one common DRAM interface. New developments in IC manufacturing technologies allow 3D chip stacking, using Through-Silicon-Vias (TSVs). This enables distributed shared memory (DSM) architectures for NoC based scalable many-core architectures, providing local DRAM access for every processor tile. Scalability, sophisticated dependability concepts and suitable programming models are essential requirements for successfull introduction and application of these new architectures.
In this presentation we will approach the whole topic area from the point of view of application mapping under mixed criticality constraints. From this perspective we will draw conclusions on necessary implications related to NoC properties, dependability concepts and application deployment on many core architectures.
Host: ESLAB - 4.4.2013: guest lecture: M.Sc. Markus Stocker (UEF)
“Wavellite: A software framework for the representation of knowledge about real-world phenomena observable by a sensor network”
Host: DS Lab - 17.–18.1., 25.–27.11.2013: research visit: M.Sc. Markus Stocker (UEF)
Host: DS Lab - 17.–18.1., 12.–13.9., 25.–27.11.2013: research visit: Dr Mauno Rönkkö (UEF)
Host: DS Lab - 20.9.2012: guest lecture: Olli-Pekka Lehto (CSC - IT Center for Science)
Future of High Performance Computing Resources at CSC
Olli-Pekka Lehto from CSC - IT Center for Science will give a presentation of the Cray Cascade supercomputer, which was selected as the next generation national supercomputing resource.
Host: Mats Aspnäs - 10.–31.8.2012: research visit: Prof. Gheorghe Stefanescu (University of Bucharest, Romania)
Gheorghe Stefanescu is a professor of Computer Science at University of Bucharest and the head of their Department of Computer Science. His research interests include parallel and distributed computing, process and network algebra, semantics of programming languages, object-oriented programming, algebraic and categorial logic, applications of category theory in logic and computer science.
Host: Luigia Petre - 15.8.2012: guest talk: Dr. Dejan Vuokbratovic (University of Novi Sad, Serbia)
Fountain Codes and Applications
Invented about a decade ago, fountain (or rateless) codes still attract a lot of attention due to their efficiency, flexibility and versatility. In this talk, we shortly review the basic properties of fountain codes and some of their interesting applications that include fountain code design for multimedia delivery, distributed storage and multiple access control deployed as part of various real-world packet-based network protocols.
Host: Kristian Nybom - 10.8.2012: guest talk: Prof. Maurizio Palesi (Kore University, Italia)
Some Research Topics on Networks on Chip: Routing Algorithms, Low Power, and Fault Tolerance
Host: Masoud Daneshtalab
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