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Department: Any ÅAU / Department of Information Technologies UTU / Department of Information Technology UTU / Department of Mathematics and Statistics UTU / Turku School of Economics, Institute of Information Systems Sciences

Research Unit: Any Algorithmics and Computational Intelligence Group (ACI) Biomathematics Research Unit (BIOMATH) Communication Systems (ComSys) Computational Biomodeling Laboratory (Combio Lab) Data Mining and Knowledge Management Laboratory Distributed Systems Laboratory (DS Lab) Embedded Computer and Electronic Systems (ECES) Embedded Systems Laboratory (ESLAB) FUNDIM, Fundamentals of Computing and Discrete Mathematics Institute for Advanced Management Systems Research (IAMSR) Learning and Reasoning Lab Software Construction Laboratorium Software Development Laboratory (SwDev) Software Engineering Laboratory (SE Lab) Turku BioNLP Group Turku Optimization Group (TOpGroup) UTU Information Systems Science (ISS)

Publication type: Any Monographs Edited books Edited special issues of journals Edited proceedings Articles in journals Articles in proceedings Chapters in edited books Ph.D. thesis Lic. thesis Technical reports

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Edited proceedings (1):

• Joona Marku, Kati Virtanen, Janne Maunu, Jonne Poikonen, Ari Paasio (Eds.), Current Mismatch and Nonlinearity Compensation in Mixed-Mode Array Processors, 2008.

Articles in journals (3):

• Jonne Poikonen, Mika Laiho, Ari Paasio, Lauri Koskinen, Kari Halonen, An Analog Processor Array Implementing Interconnect-Efficient Reference Data Shift and SAD/SSD Extraction for Motion Estimation. EURASIP Journal on Advances in Signal Processing 2009, 11, 2009.
• Jonne Poikonen, Ari Paasio, An 8x8 Cell Analog Order-Statistic-Filter Array With Asynchronous Grayscale Morphology in 0.13um CMOS. IEEE Transactions on Circuits and Systems I: Regular Papers 56(8), 1541-1553, 2009.
• Jonne Poikonen, Ari Paasio, A Ranked Order Filter Implementation for Parallel Analog Processing. IEEE Transactions on Circuits and Systems - I 51, 974-987, 2004.

Articles in proceedings (40):

• Olli Lahdenoja, Tero Säntti, Jonne Poikonen, Mika Laiho, Ari Paasio, Characterizing Spatters in Laser Welding of Thick Steel Using Motion Flow Analysis. In: Erkki Oja, Matti Pietikäinen (Eds.), SCIA : 18th Scandinavian Conference on Image Analysis, Springer Lecture Notes in Computer Science (LNCS), 675–686, Springer Berlin Heidelberg, 2013.
• Lauri Koskinen, Jonne Poikonen, Mika Laiho, Ari Paasio, Rate-Distortion Performance Analysis of an Analog Motion Estimation Array. In: IEEE International Workshop on Cellular Nanoscale Networks and Applications, 2010.
• Olli Lahdenoja, Jonne Poikonen, Mika Laiho, Extracting Local Binary Patterns with MIPA4k Vision Processor. In: IEEE International Workshop on Cellular Nanoscale Networks and Applications, 2010.
• Mika Laiho, Jonne Poikonen, Ari Paasio, Object Segmentation and Tracking with Asynchronous Grayscale and Binary Wave Operations on the MIPA4k. In: IEEE International Workshop on Cellular Nanoscale Networks and Applications, 2010.
• Eero Lehtonen, Jussi Poikonen, Jonne Poikonen, Mika Laiho, Grayscale CNN Computation of Boolean Functions. In: IEEE Latin American Symposium on Circuits and Systems, 2010.
• Jonne Poikonen, Mika Laiho, Ari Paasio, Anisotropic Fltering with a Resistive Fuse Network on the MIPA4k Processor Array. In: IEEE International Workshop on Cellular Nanoscale Networks and Applications, 2010.
• Markus Grönholm, Jonne Poikonen, Mika Laiho, A Ring-Oscillator-Based Active Quenching and Active Recharge Circuit for Single Photon Avalanche Diodes. In: Proceedings of the European Conference on Circuit Theory and Design, ECCTD 2009, 5-8 , 2009.
• Mika Laiho, Jonne Poikonen, Ari Paasio, Space-Dependent Binary Image Processing Within a 64x64 Mixed-Mode Array Processor. In: Proceedings of the European Conference on Circuit Theory and Design, ECCTD 2009, 189-192 , 2009.
• Mika Laiho, Jonne Poikonen, Peter Virta, Ari Paasio, Live Demonstration: MIPA4k: A 64×64 Cell Mixed-Mode Image Processor Array. In: Proc. of theIEEE International Symposium on Circuits and Systems, 2009. ISCAS 2009. , 1931-1931 , 2009.
• Joona Marku, Jonne Poikonen, Ari Paasio, Temperature Compensation in Combination Selection Based Mismatch Calibration. In: Proc. of the IEEE International Symposium on Circuits and Systems, 2009. ISCAS 2009. , 1589-1592 , 2009.
• Joona Marku, Jonne Poikonen, Ari Paasio, Temperature Behavior of Combination Selection Based Mismatch Calibration with 65 nm CMOS Technology. In: Proc. of the IEEE International System on Chip Conference, 2009. SOCC 2009. , 2009.
• Jonne Poikonen, Mika Laiho, Ari Paasio, MIPA4k: A 64×64 Cell Mixed-Mode Image Processor Array. In: Proc. of the IEEE International Symposium onCircuits and Systems, 2009. ISCAS 2009. , 1927-1930, 2009.
• Jonne Poikonen, Mika Laiho, Ari Paasio, Locally Adaptive Image Sensing with the 64x64 Cell MIPA4k Mixed-Mode Image Processor Array. In: Proceedings of the European Conference on Circuit Theory and Design, ECCTD 2009, 93-96, 2009.
• Mika Laiho, Jonne Poikonen, Ari Paasio, Kari Halonen, Centroiding and Classification of Objects Using a Processor Array with a Scalable Region of Interest. In: IEEE International Symposium on Circuits and Systems 2008, ISCAS 2008, 2008.
• Mika Laiho, Jonne Poikonen, Kati Sairanen (Virtanen), Ari Paasio, Self-Adapting Compressive Image Sensing Scheme. In: 11th International Workshop on Cellular Neural Networks and Their Applications, 2008. CNNA 2008. , 2008.
• Mika Laiho, Jonne Poikonen, Peter Virta, Ari Paasio, A 64x64 Cell Mixed-Mode Array Processor Prototyping System. In: 11th International Workshop on Cellular Neural Networks and Their Applications, 2008. CNNA 2008. , 2008.
• Joona Marku, Kati Virtanen, Janne Maunu, Jonne Poikonen, Ari Paasio, Current Mismatch and Nonlinearity Compensation in Mixed-Mode Array Processors. In: 11th International Workshop on Cellular Neural Networks and their Applications, 2008.
• Jonne Poikonen, Mika Laiho, Ari Paasio, Lauri Koskinen, Kari Halonen, Interconnect-Efficient Reference Data Shift for Optimized Analog Motion Estimation. In: 11th International Workshop on Cellular Neural Networks and Their Applications, 2008. CNNA 2008. , 2008.
• Kati Virtanen, Janne Maunu, Jonne Poikonen, Ari Paasio, A 12-bit Current-Steering DAC with Calibration by Combination Selection. In: 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007, New Orleans, USA, 2007.
• Janne Maunu, Mikko Pänkäälä, Joona Marku, Jonne Poikonen, Mika Laiho, Ari Paasio, Current Source Calibration by Combination Selection of Minimum Sized Devices. In: 2006 IEEE International Symposium on Circuits and Systems, ISCAS 2006, Kos, Greece, 2006.
• Ari Paasio, Jonne Poikonen, Programmable Digital Nested CNN. In: Proceedings of the 10th IEEE International Workshop on Cellular Neural Networks and their Applications (CNNA) 2006, 2006.
• Jonne Poikonen, Ari Paasio, On the Topographic Equivalence Between Voltage Mode and Current Mode Ranked Order Filters for Array Processors. In: 2006 IEEE International Symposium on Circuits and Systems, ISCAS 2006, Kos, Greece, 2006.
• Olli Lahdenoja, Jonne Poikonen, Ari Paasio, Effect of Mismatch on a Ranked-Order Extractor Array. In: Proceedings of the 2005 IEEE International Symposium on Circuits and Systems, ISCAS'05, 2005.
• Jonne Poikonen, Ari Paasio, Rank Identification for an Analog Ranked Order Filter. In: Proceedings of the 2005 IEEE International Symposium on Circuits and Systems, ISCAS'05, 2005.
• Jonne Poikonen, Ari Paasio, Mismatch-Tolerant Asynchronous Grayscale Morphological Reconstruction. In: Proceedings of the 9th IEEE International Workshop on Cellular Neural Networks and their Applications, CNNA 2005, 2005.
• Laura Vesalainen, Jonne Poikonen, Ari Paasio, A Gray-Coded Digital-to-Analog Converter for a Mixed-Mode Processor Array . In: Proceedings of the 2005 IEEE International Symposium on Circuits and Systems, ISCAS'05, 2005.
• Laura Vesalainen, Jonne Poikonen, Ari Paasio, A Modified In-Cell ADC using Ranked Order Extraction. In: Proceedings of the 9th IEEE International Workshop on Cellular Neural Networks and their Applications, CNNA 2005, 2005.
• Mikko Pänkäälä, Jonne Poikonen, Laura Vesalainen, Ari Paasio, Realization of an Analog Current-Mode 2-Dimensional DCT. In: ISCAS '04. Proceedings of the 2004 International Symposium on Circuits and Systems, 2004. , 2004.
• Mikko Pänkäälä, Jonne Poikonen, Laura Vesalainen, Ari Paasio, An Analog Current-Mode 2-D DCT Implementation. In: Norchip 2004, 2004.
• Jonne Poikonen, Ari Paasio, Current Controlled Resistive Fuse Implementation in a Mixed-Mode Array Processor Core. In: Cellular Neural Networks and their Applications, CNNA 2004, 2004.
• Laura Vesalainen, Jonne Poikonen, Ari Paasio, A Fuzzy Unit for a Mixed-Mode Array Processor. In: Cellular Neural Networks and their Applications, CNNA 2004, 2004.
• Laura Vesalainen, Jonne Poikonen, Ari Paasio, A Current-Mode Implementation for Trapetzoidal Fuzzy Membership Function. In: BEC 2004, 2004.
• Laura Vesalainen, Jonne Poikonen, Mikko Pänkäälä, Ari Paasio, A Gray-Code Current-Mode ADC for Mixed-Mode Cellular Computer. In: ISCAS '04. Proceedings of the 2004 International Symposium on Circuits and Systems, 2004., 2004.
• Laura Vesalainen, Jonne Poikonen, Mikko Pänkäälä, Ari Paasio, First Measurement Results of a Gray-Code Current-Mode ADC. In: Norchip 2004, 2004.
• Ari Paasio, Mika Laiho, Jonne Poikonen, Asko Kananen, Kari Halonen, A 32 x 32 Cellular Test Chip Targeting New Functionalities. In: III, 506-509, 2003.
• Ari Paasio, Jonne Poikonen, An Implementation Oriented Coding System for Nested CNNs. In: European Conference on Circuit Theory and Design, 2003.
• Ari Paasio, Jonne Poikonen, A Compact CMOS Realization for Nested CNNs. In: European Conference on Circuit Theory and Design, 2003.
• Jonne Poikonen, Ari Paasio, Robustness Analysis of a Physical Multi-Nested CNN Implementation. In: European Conference on Circuit Theory and Design, 2003.
• Jonne Poikonen, Ari Paasio, An Area-Efficient Full-Wave Current Rectifier for Analog Array Processing. In: International Symposium on Circuits and Systems, V, 757-760, 2003.
• Jonne Poikonen, Ari Paasio, Implementing Grayscale Morphological Operators with a Compact Ranked Order Extractor Circuit. In: Proceedings of the 7th IEEE International Workshop on Cellular Neural Networks and their Applications, 646-653, Word Scientific, 2002.

Ph.D. thesis (1):

• Jonne Poikonen, Absolute Value Extraction and Order Statistic Filtering for a Mixed-Mode Array Image Processor. TUCS Dissertations 80. Turku Centre for Computer Science, 2006.

Other (1):

• misc: Paasio, Ari and Poikonen, Jonne: Suomalainen patentti, FI 115807 - Virran tasasuuntaava kytkentä, sen käyttö sekä menetelmä rinnakkaisprosessoriverkossa