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Architectural Modeling of Pixel Readout Chips Velopix and Timepix3
Tuomas Poikela, Juha Plosila, Tomi Westerlund, Jan Buytaert, Michael Campbell, Xavier Llopart, Richard Plackett, Ken Wyllie, Martin van Beuzekom, Vladimir Gromov, Ruud Kluit, Francesco Zappon, Vlad Zivkovic, Architectural Modeling of Pixel Readout Chips Velopix and Timepix3. In: Topical Workshop on Electronics for Particle Physics 2011 (TWEPP-11), 7, 1-7, Journal of Instrumentation, 2012.
http://dx.doi.org/10.1088/1748-0221/7/01/C01093
Abstract:
We examine two digital architectures for front end pixel readout chips, Velopix and Timepix3. These readout chips are developed for tracking detectors in future high energy physics experiments. They must incorporate local intelligence in pixels for time-over-threshold measure-ment and sparse readout. In addition, Velopix must be immune to single-event upsets in its digital logic. The most important requirements for both chips are pixel size, timing resolution, low power and high-speed sparse readout. We describe the transaction level architectural models of the chips using SystemVerilog. The correctness of the models is ensured using Open Veriļ¬cation Methodology. We will also discuss the advantages gained from transaction level modeling.
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BibTeX entry:
@INPROCEEDINGS{inpPoPlWeBuCaLlPlWyvaGrKlZaZiBrDeFaKr12a,
title = {Architectural Modeling of Pixel Readout Chips Velopix and Timepix3},
booktitle = {Topical Workshop on Electronics for Particle Physics 2011 (TWEPP-11)},
author = {Poikela, Tuomas and Plosila, Juha and Westerlund, Tomi and Buytaert, Jan and Campbell, Michael and Llopart, Xavier and Plackett, Richard and Wyllie, Ken and van Beuzekom, Martin and Gromov, Vladimir and Kluit, Ruud and Zappon, Francesco and Zivkovic, Vlad},
volume = {7},
publisher = {Journal of Instrumentation},
pages = {1-7},
year = {2012},
keywords = {VLSI Circuits; Digital electronic circuits; Simulation methods and programs.},
}
Belongs to TUCS Research Unit(s): Embedded Computer and Electronic Systems (ECES)