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Department: Any ÅAU / Department of Information Technologies UTU / Department of Information Technology UTU / Department of Mathematics and Statistics UTU / Turku School of Economics, Institute of Information Systems Sciences

Research Unit: Any Algorithmics and Computational Intelligence Group (ACI) Biomathematics Research Unit (BIOMATH) Communication Systems (ComSys) Computational Biomodeling Laboratory (Combio Lab) Data Mining and Knowledge Management Laboratory Distributed Systems Laboratory (DS Lab) Embedded Computer and Electronic Systems (ECES) Embedded Systems Laboratory (ESLAB) FUNDIM, Fundamentals of Computing and Discrete Mathematics Institute for Advanced Management Systems Research (IAMSR) Learning and Reasoning Lab Software Construction Laboratorium Software Development Laboratory (SwDev) Software Engineering Laboratory (SE Lab) Turku BioNLP Group Turku Optimization Group (TOpGroup) UTU Information Systems Science (ISS)

Publication type: Any Monographs Edited books Edited special issues of journals Edited proceedings Articles in journals Articles in proceedings Chapters in edited books Ph.D. thesis Lic. thesis Technical reports

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Articles in journals (5):

• Matti Kaisti, Ville Rantala, Tapio Mujunen, Sami Hyrynsalmi, Kaisa Könnölä, Tuomas Mäkilä, Teijo Lehtonen, Agile Methods for Embedded Systems Development - a Literature Review and a Mapping Study. EURASIP Journal of Embedded Systems 2013(15), 1–16, 2013.
• Ville Rantala, Teijo Lehtonen, Pasi Liljeberg, Juha Plosila, Analysis of Monitoring Structures for Network-on-Chip: A Distributed Approach. International Journal of Embedded and Real-Time Communication Systems (IJERTCS) 2(1), 49-67, 2011.
• Teijo Lehtonen, David Wolpert, Pasi Liljeberg, Juha Plosila, Paul Ampadu, Self-Adaptive System for Addressing Permanent Errors in On-Chip Interconnects. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18(4), 527–540, 2010.
• Teijo Lehtonen, Pasi Liljeberg, Juha Plosila, Online Reconfigurable Self-Timed Links for Fault Tolerant NoC. VLSI Design 2007, 13, 2007.
• Ethiopia Nigussie, Teijo Lehtonen, Sampo Tuuna, Juha Plosila, Jouni Isoaho, High-Performance Long NoC Link Using Delay-Insensitive Current-Mode Signaling. VLSI Design 2007, Article ID 46514, 2007.

Articles in proceedings (12):

• Ville Rantala, Teijo Lehtonen, Pasi Liljeberg, Juha Plosila, Analysis of Status Data Update in Dynamically Clustered Network-on-Chip Monitoring. In: César Benavente-Peces, Joaquim Filipe (Eds.), International Conference on Pervasive and Embedded Computing and Communication Systems (PECCS 2011), 493-496, INSTICC, 2011.
• Teijo Lehtonen, Pasi Liljeberg, Juha Plosila, Analysis of Fault Tolerant Deadlock-free Routing Algorithms for Mesh NoCs. In: 3rd Workshop on Diagnostic Services in Network-on-Chips, DSNOC '09, 54–57, 2009.
• Teijo Lehtonen, Pasi Liljeberg, Juha Plosila, Fault Tolerance Analysis of Distributed Algorithms for Mesh Networks-on-Chip. In: 9th International Symposium on Signals, Circuits and Systems, ISSCS 2009, 149-152, IEEE, 2009.
• Ville Rantala, Teijo Lehtonen, Pasi Liljeberg, Juha Plosila, Dual-NI Architectures for Fault Tolerant NoC. In: Design, Automation and Test in Europe DATE Conference 2009, Digest of the Workshop on Diagnostic Services in Network-on-Chips, 2009.
• Ville Rantala, Teijo Lehtonen, Pasi Liljeberg, Juha Plosila, Multi Network Interface Architectures for Fault Tolerant Network-on-Chip. In: International Symposium on Signals, Circuits and Systems (ISSCS '09), 145-148, IEEE, 2009.
• Ville Rantala, Teijo Lehtonen, Pasi Liljeberg, Juha Plosila, Hybrid NoC with Traffic Monitoring and Adaptive Routing for Future 3D Integrated Chips. In: Design Automation Conference DAC 2008, Digest of the Workshop on Diagnostic Services in Network-on-Chips, 2008.
• Ville Rantala, Teijo Lehtonen, Pasi Liljeberg, Juha Plosila, Distributed Traffic Monitoring Methods for Adaptive Network-on-Chip. In: Norchip Conference, 233-236, IEEE, 2008.
• Teijo Lehtonen, Pasi Liljeberg, Juha Plosila, Self-Timed NoC Links Using Combinations of Fault Tolerance Methods. In: Design, Automation and Test in Europe DATE Conference 2007, Digest of the Workshop on Diagnostic Services in Network-on-Chips, 327-332, 2007.
• Teijo Lehtonen, Pasi Liljeberg, Juha Plosila, Analysis of Forward Error Correction Methods for Nanoscale Networks-On-Chip. In: Proceedings of the 2nd International Conference on Nano-Networks (Nano-Net 2007), 5 pages, 2007.
• Teijo Lehtonen, Pasi Liljeberg, Juha Plosila, Fault Tolerance Analysis of NoC Architectures. In: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2007), 361-364, 2007.
• Teijo Lehtonen, Pekka Rantala, Petri Isomäki, Juha Plosila, Jouni Isoaho, An Approach for Analysing and Improving Fault Tolerance in Radio Architectures. In: Proceedings of IEEE International Symposium on Circuits and Systems ISCAS 2006, 3414-3417, IEEE, 2006.
• Pekka Rantala, Teijo Lehtonen, Jouni Isoaho, Juha Plosila, Fault-Tolerant Routing Approach for Reconfigurable Networks-on-chip. In: Proceedings of the International Symposium on System-on-Chip (SoC) 2006, Tampere, Finland, November 13-16, 2006, 2006.

Ph.D. thesis (1):

• Teijo Lehtonen, On Fault Tolerance Methods for Networks-on-Chip. TUCS Dissertations 122. Turku Centre for Computer Science, 2009.

Licenciate thesis (1):

• Teijo Lehtonen, On Designing Fault Tolerant Nanoscale Systems. 2007.

Technical reports (3):

• Teijo Lehtonen, Ville Rantala, Pasi Liljeberg, Juha Plosila, FANSI: Fault Tolerant Network-on-Chip Simulator. TUCS Technical Reports 935, Turku Centre for Computer Science, 2009.
• Ville Rantala, Teijo Lehtonen, Juha Plosila, Network on Chip Routing Algorithms. TUCS Technical Reports 779, Turku Centre for Computer Science, 2006.
• Teijo Lehtonen, Juha Plosila, Jouni Isoaho, On Fault Tolerance Techniques towards Nanoscale Circuits and Systems. TUCS Technical Reports 708, Turku Centre for Computer Science, 2005.